System Design Using FPGA

Course: System Design using FPGA

Code: 3ФЕИТ05019

ECTS points: 6 ECTS

Number of classes per week: 3+0+0+3

Lecturer: Prof. Dr. Katerina Raleva

Course Goals (acquired competencies): The course offers a thorough knowledge in digital design using VHDL as a hardware description language. After finishing the course, the student will be able to design complex digital circuits and systems using VHDL and to implement the design (to synthesize) on a FPGA platform.

Course Syllabus: Digital VLSI design and the need for hardware description languages (HDL). Technologies fo fabrication of integrated circuits. Programmable technologies. Complex progammable logic devices (CPLD) - architectures, programmable interconnections and macrocell structure. Field Programmable Gate Array (FPGA) – architecture, configuration logic blocs and switching matrix.Commercial  FPGA architectures.  VHDL structure - entity and architecture. Ports and signals. Concurrent and sequential statements. VHDL description  of combinational and sequential logic. Simulation versus synthesis.  Functions and procedures in VHDL.  Memory components and memory controllers.Distributed and embedded RAM in FPGA. Using IP Core (Intellectual Property)in FPGA design. Hierarhy in designing large digital systems. RTL (Register Transfer Level) design – definition,types of RTL design. Steps in RTL designing. Optimization of RTL design. RTL design with HDL. Syntesis and implementation of design. Datapath optimization. Hardware-software co-design.

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